Bias circuitry in various integrated circuits (“IC's”) undesirably increases the size and complexity of the IC. In this regard, the cost to produce an IC is generally proportional to the size of the IC. Thus, substantial cost savings may be obtained when a mass produced IC is designed with a smaller chip area. Furthermore, complex IC layouts often take longer to design and unduly restrict the layout of the IC and the layout of devices connecting to the IC.
In various IC's, a substantial portion of the circuitry layout comprises bias feed circuitry. Bias feed circuitry may serve as both a DC power supply path, providing biasing current to transistors on the IC, and as a RF block (“bias choke”). Bias circuitry may become undesirably large in IC's that have high current DC bias and/or high frequency signals. The high current may result in large bias circuitry because the current carrying line is configured to be wide enough to suitably carry the current. Additionally, one or more bias feed line may be incorporated into the chip to share the current carrying duty and thus reduce the width of each bias feed line. With regard to performing the RF blocking function, bias feeds typically require a suitable length trace. In order to fit the bias feed on the chip and maintain a suitable length trace, the traces are often laid out with turns and bends. Unfortunately, wider bias feed lines typically use disproportionately large areas to make turns. Therefore, high power/high frequency IC devices typically have large bias feed sections.
These high power/high frequency characteristics exist in some IC's that amplify high frequency radio frequency (“RF”) and microwave signals. One such IC is a monolithic microwave integrated circuit (MMIC) amplifier. A MMIC is typically used to amplify high frequency RF and/or microwave signals. FIG. 1 illustrates a conventional MMIC high power amplifier (“HPA”) 100. As is typical, DC bias circuitry areas 190 occupy about 15% to 20% of the total chip area. DC bias circuitry 110 may function as both a DC power supply path to transistors 120 and an RF block (“bias choke”). In high power applications, such as the MMIC, the DC bias circuitry typically employs wide lines, e.g., 112, to accommodate the large current flow to transistors 120. Furthermore, to reduce the line width and/or supply more current, DC bias circuitry 110 is often fed from two sides, e.g., 101 and 102, splitting the current between two lines, e.g., 112 and 113. In addition to the space used to provide current from two sides of a chip, this technique undesirably places restrictions on the next higher level of circuitry to which MMIC 100 is attached. For example, MMIC 100 may be attached to a motherboard having a pair of power lines to the points of connection with the MMIC for providing power to on-chip bias lines 112 and 113.
On-chip capacitors 130 are configured for providing an RF choke. On-chip capacitors 130 are typically located at a 90 degree phase angle length from a matching and combining structure 140. The high impedance line acts as a virtual open to the RF signals, and the on-chip capacitors are configured to short residual RF signals to ground. Bias feed circuit line layouts often have turns in the lines (e.g., 108) to facilitate a suitable RF choke length between capacitors 130 and matching structures 140. However, turns in wide lines generally involve large turning radiuses and more space on the IC. Therefore, prior art bias injection techniques typically involve a lot of bias feed section space on the IC for high frequency and high current applications.
FIG. 2 illustrates the conventional MMIC 200 of FIG. 1 with DC bond wires 220 connecting DC bias circuitry 210 of MMIC 200 to the circuitry of the next higher assembly 250. For example, bond wire 220 is attached to by-pass capacitor 240.
MMICs and other similar devices are now finding applicability in consumer and manufacturing goods and thus, mass production for applications such as broadband home TV and/or internet satellite transmitters, and lasers is desirable. Therefore, it is desirable to reduce the size of the IC layouts and/or to reduce the complexity of IC layouts for more compact applications.